Charge coupled devices (CCD's) are fabricated as metal-oxide-silicon (MOS) or metal-insulated-silicon (MIS) integrated circuits wherein charges are stored on the surface of a substrate by the application of voltage pulses to storage gates to form potential wells. Signal charges may be inputted and the resultant charge packets are shifted along various points throughout the substrate of the device by the application of the proper sequence of voltage pulses to modulate the potential wells. A particular application of charge coupled devices is that of forming serial dynamic memory arrays in which the bits are recirculating and are refreshed in closed loops. They can only be accessed at fixed locations in the loop. Such CCD memories have very large storage capacities and also faster access than is provided by other serial type memories such as drums and disks.
Refresh circuitry is required to maintain the magnitude of the charge packets which would otherwise diminish due to transfer inefficiency and to regenerate an empty (or almost empty) charge packet which would otherwise be filled due to thermal dark current. Fabrication of the substrate and the means for shifting the charge packets around the substrate are well described in the prior art as illustrated by the Kosonocky U.S. Pat. Nos. 3,758,794 and 3,760,202. These patents also disclose regeneration circuits, methods and means for operating CCD's in plural phase configurations and clocking and timing means. A number of papers which discuss the application and technology of charge coupled devices include W. S. Boyle and G. E. Smith, "Charge-Coupled Devices--A New Approach to MIS Device Structure" IEEE Spectrum, July, 1971; Altman, "The New Concept for Memory and Imaging: Charge Coupling" Electronics, June 21, 1971.
In addition to the advantages of shorter access times and higher storage density, CCD's have the advantage over disk and drum type memories of compactness and high relaibility because there are no moving parts. As a result, CCD memories have a distinct advantage in cost performance both in multilevel memory hierarchies and when used as individual memories.
The power dissipation and access time of a CCD memory system is dependent upon the memory organization. If access time is used to distinguish between various CCD organizations, two classes can be defined--slow access and fast access. The slow access class is represented by the serial-parallel-serial (SPS) structure and also the single-loop serpentine structure. The fast access class has two types of prior art organizations. The first type is the self-recirculating loop type with an on-chip decoder. These can be formed into a series of loops on a chip with each loop being assigned an address so that the individual loops can be accessed randomly. The bits in the loop are shifted constantly. In this organization, the power dissipation is high but the total area per bit is small. The second type of fast access memories is the line-address-random-access-memory (LARAM). In this organization, the bits in a track are shifted only if that particular track is being refreshed or accessed. All the signal bits are regenerated by a single refresh amplifier for a block of registers. Therefore, when one track is being refreshed no read/write or refreshing operation can be performed in any other track in the same block. This leads to an increase in latency. However, power dissipation is low.
The above described organizations which exist in the prior art are not the only CCD memory organizations possible. Particular organizational designs are characterized by three parameters--the control over the read/write data path, the control over the refresh data path and the control of the clock path. By varying these different parameters, new organizational designs can be achieved which exhibit reduced power dissipation and/or service time.
It is then an object of the present invention to provide a variety of improved fast access charge coupled device memory organizations.
It is another object of the present invention to provide a variety of improved power dissipation charge coupled device memory organizations.
It is another object of the present invention to provide a variety of improved fast access memory organizations for a single CCD semiconductor chip.
It is another object of the present invention to provide a variety of improved power dissipation memory organizations for a single CCD semiconductor chip.
It is still a further object of the present invention to provide fast access CCD memory organizations which have reduced power dissipation and service time.